The entire disclosure of Japanese Patent Application No. 2008-153961, filed Jun. 12, 2008 is expressly incorporated by reference herein.
1. Technical Field
The present invention relates to a semiconductor integrated circuit that has a built-in non-volatile memory in which data is electrically writable and erasable.
2. Related Art
Erasable Programmable Read-Only Memory (EPROM) devices are widely used as non-volatile memory devices which allow repeated erasing and writing-in of data. Types of EPROM include Ultra-Violet Erasable Programmable Read Only Memory (UV-EPROM) and Electrically Erasable Programmable Read Only Memory (EEPROM). Memory content of UV-EPROM is erased by ultraviolet light while the memory content of EEPROM is erased electrically. EEPROM is convenient to use due to the above property. However, there is a problem that the physical size of the memory device increases in order to store a large amount of data. Therefore, it is required to reduce the size of the EEPROM memory cell. At the same time, it is required to simplify the manufacturing process of semiconductor integrated circuits with a built-in EEPROM.
FIGS. 6A and 6B are drawings illustrating a structure of an EEPROM memory cell in a semiconductor integrated circuit according to related art. FIG. 6A is a plan view and FIG. 6B is a sectional view of FIG. 6A taken along the line VI-VI. Illustration of an interlayer insulating film is omitted in FIGS. 6A and 6B in order to indicate a positional relationship of conductors.
As shown in FIG. 6B, a p-type semiconductor substrate 110 includes thermal oxide films 111a and 111b, lightly doped n-type impurity diffused region 112, and n-type impurity diffused regions 113a, 113b, 114a, and 114b. Here, the impurity diffused regions 113a and 113b respectively constitute a source/drain of an n-channel MOS transistor Q11 (sensing transistor), and the impurity diffused regions 114a and 114b respectively constitute a source/drain of an n-channel MOS transistor Q12 (selecting transistor).
An upper electrode 132 and a floating gate electrode 131 as a polysilicon underlayer are formed over the semiconductor substrate 110, respectively separated by a gate insulating film 121 and by a tunnel film 122. The upper electrode 132, the tunnel film 122 and the impurity diffused region 112 constitute a capacitor CA. A gate electrode 141 (word line WL) made of a polysilicon layer is formed over the semiconductor substrate 110 with a gate insulating film 123 interposed therebetween.
As shown in FIG. 6A, a lightly doped n-type impurity diffused region 115 is formed in the semiconductor substrate 110. An upper electrode 133 as a polysilicon underlayer is formed over the semiconductor substrate 110 with the interlayer insulating film interposed therebetween. The upper electrode 133, the interlayer insulating film, and the impurity diffused region 115 constitute a capacitor CB.
Moreover, n-type impurity diffused regions 116a and 116b are formed in the semiconductor substrate 110. The n-type impurity diffused region 116a is coupled to the impurity diffused region 115. Here, the impurity diffused regions 116a and 116b respectively constitute a source/drain of an n-channel MOS transistor Q13 (selecting transistor). A word line 141 constitutes a gate electrode of the MOS transistor Q13.
Moreover, wirings 151, 152, and 153 made of an aluminum wiring layer are formed over the semiconductor substrate 110, separated by the interlayer insulating film. The wirings 151, 152, and 153 are respectively electrically coupled to the impurity diffused regions 113a, 114b, and 116b. 
In this structure, the capacitors CB and CA are coupled in series between the source/drain of the transistor Q13 (impurity diffused region 116a) and the source/drain of the transistor Q12 (impurity diffused region 114a), and a connection point between the capacitors CB and CA (upper electrodes 132 and 133) is coupled to the floating gate electrode 131 of the transistor Q11.
Applying a high-level selection signal and a prescribed control voltage respectively to the word line 141 and to the serial connection of the capacitors CB and CA via transistors Q13 and Q12 causes the Fowler-Nordheim (FN) tunneling current to flow through the tunnel film 122, and one of positive and negative charges are accumulated in the upper electrodes 132 and 133. Consequently, information is stored in the memory cell. This information is sensed when the transistor Q11 is fixed to one of an on-state and an off-state. This transistor Q11 includes the floating gate electrode 131 coupled to the upper electrodes 132 and 133.
However, in this structure shown in FIGS. 6A and 6B, the memory cell size increases since the capacitors CA and CB are arranged in a planar configuration. Moreover, the process of forming the gate insulating film 121 and the tunnel film 122 needs to be handled separately from the process of forming the gate insulating film 123, thereby complicating the manufacturing process of the semiconductor integrated circuit that includes a built-in EEPROM.
As an example of related art, JP-A-2000-12709 discloses a non-volatile semiconductor memory which operates with reduced voltages for writing-in and erasing. This non-volatile semiconductor memory includes a trench in a semiconductor substrate, and has a higher coupling ratio realized by an expanded area in which the floating gate electrode opposes the control gate electrode. In this non-volatile semiconductor memory, the trench has two different widths. In a narrow trench region, an insulating layer is entirely buried into the trench, and in a wide trench region, the insulating layer is buried inside the trench in a concaved shape. The floating gate electrode is formed on a channel region of an active region with a gate insulating film therebetween, as well as inside the concave of the insulating layer. The control gate electrode is formed on the floating gate electrode across the inside and outside of the concave. However, forming the trench inside the semiconductor substrate complicates the manufacturing process of the non-volatile semiconductor memory.
As another example of related art, JP-A-2002-246485 discloses a non-volatile semiconductor storage device which improves a coupling ratio of a floating gate electrode and a control gate electrode. This non-volatile semiconductor storage device includes: a semiconductor substrate with a main surface; a floating gate electrode including a first conductive film formed on the main surface with a tunnel insulating film therebetween, and a second conductive film deposited on the first conductive film, the second conductive film having a convex (wall); an insulating film formed covering the second conductive film; and a control gate electrode formed on the insulating film. However, forming the floating gate electrode with two conductive films complicates the manufacturing process of the non-volatile semiconductor storage device.